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DATA SHEET
MOS INTEGRATED CIRCUIT
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
16-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
The
PD78F4216A/78F4218A
and
78F4216AY/78F4218AY
are
products
of
PD784216A/784218A,
784216AY/784218AY Subseries in the 78K/IV Series. The PD78F4216A/78F4218A have flash memory in place of the internal ROM of the PD784216A/784218A. The incorporation of flash memory allows a program to be written or erased while mounted on the target board. The PD78F4216AY/78F4218AY are based on the PD78F4216A/78F4218A Subseries with the addition of a multimaster-supporting I2C bus interface. Detailed function descriptions are provided in the following user's manuals. Be sure to read them before designing. PD784216A, 784216AY Subseries User's Manual Hardware: U13570E PD784218A, 784218AY Subseries User's Manual Hardware: U12970E 78K/IV Series User's Manual Instructions: U10905E
FEATURES
* Pin compatible with the mask ROM products * Flash memory: 128 KB (PD78F4216A/78F4216AY) 256 KB (PD78F4218A/78F4218AY) * Internal RAM: 8,192 bytes (PD78F4216A/78F4216AY) 12,800 bytes (PD78F4218A/78F4218AY) * Supply voltage: VDD = 1.9 to 5.5 V
APPLICATIONS
Cellular phones, PHS, cordless telephones, CD-ROM, AV equipment
Unless otherwise specified, references in this document to the PD78F4218AY refer to the PD78F4216A, 78F4218A, 78F4216AY, and 78F4218AY.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. U14125EJ1V0DS00 (1st edition) Date Published November 2000 N CP(K) Printed in Japan
2000
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
ORDERING INFORMATION
Part Number Package 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) Internal ROM (Bytes) 128 K 128 K 256 K 256 K 128 K 128 K 256 K 256 K Internal RAM (Bytes) 8,192 8,192 12,800 12,800 8,192 8,192 12,800 12,800
PD78F4216AGC-8EU PD78F4216AGF-3BA PD78F4218AGC-8EU PD78F4218AGF-3BA PD78F4216AYGC-8EU PD78F4216AYGF-3BA PD78F4218AYGC-8EU PD78F4218AYGF-3BA
2
Data Sheet U14125EJ1V0DS00
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
78K/IV SERIES LINEUP
: Products in mass-production : Products under development Supports I2C bus Supports multimaster I2C bus
PD784038Y PD784038
PD784225Y PD784225
80-pin, ROM correction added Supports multimaster I2C bus
Standard models
PD784026
Enhanced A/D converter, 16-bit timer, and power management
Enhanced internal memory capacity Pin-compatible with the PD784026 Supports multimaster I2C bus
PD784216AY PD784216A
100-pin, enhanced I/O and internal memory capacity
PD784218AY PD784218A
Enhanced internal memory capacity, ROM correction added
PD784054 PD784046
ASSP models
PD784956A
For DC inverter control
On-chip 10-bit A/D converter
PD784967
Enhanced functions of the PD784938A, enhanced I/O and internal memory capacity.
PD784938A
Enhanced functions of the PD784908, enhanced internal memory capacity, ROM correction added. Supports multimaster I2C bus
PD784908
On-chip IEBusTM controller
PD784928Y PD784915
Software servo control On-chip analog circuit for VCRs Enhanced timer
PD784928
Enhanced functions of the PD784915
PD784976
On-chip VFD controller/driver
Data Sheet U14125EJ1V0DS00
3
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
OVERVIEW OF FUNCTIONS (1/2)
Part Number Item Number of basic instructions (mnemonics) General-purpose registers Minimum instruction execution time 113 8 bits x 16 registers x 8 banks, or 16 bits x 8 registers x 8 banks (memory mapping) * 160 ns/320 ns/640 ns/1,280 ns/2,560 ns (@fXX = 12.5 MHz operation with main system clock) * 61 s (@fXT = 32.768 kHz operation with subsystem clock) 128 KB 8,192 bytes 256 KB 12,800 bytes
PD78F4216A, PD78F4216AY
PD78F4218A, PD78F4218AY
Internal memory Memory space I/O ports
Flash memory RAM
1 MB with program and data spaces combined Total CMOS input CMOS I/O N-ch open-drain I/O 86 8 72 6 70 22 6 4 bits x 2 or 8 bits x 1 Timer/event counter: (16-bit) Timer counter x 1 Pulse output Capture/compare register x 2 * PPG output * Square wave output * One-shot pulse output Pulse output * PWM output * Square wave output Pulse output * PWM output * Square wave output Pulse output * PWM output * Square wave output Pulse output * PWM output * Square wave output Pulse output * PWM output * Square wave output Pulse output * PWM output * Square wave output
Pins with additional functionsNote 1
Pins with pull-up resistor LED direct drive output Middle-voltage pin
Real-time output port Timer/event counter
Timer/event counter 1: Timer counter x 1 (8-bit) Compare register x 1 Timer/event counter 2: Timer counter x 1 (8-bit) Compare register x 1 Timer/event counter 5: Timer counter x 1 (8-bit) Compare register x 1 Timer/event counter 6: Timer counter x 1 (8-bit) Compare register x 1 Timer/event counter 7: Timer counter x 1 (8-bit) Compare register x 1 Timer/event counter 8: Timer counter x 1 (8-bit) Compare register x 1 Serial interface A/D converter D/A converter
* UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator) 2 * CSI (3-wire serial I/O, multimaster supporting I C busNote 2): 1 channel 8-bit resolution x 8 channels 8-bit resolution x 2 channels
Notes 1. Pins with additional functions are included with the I/O pins. 2. PD78F4216AY, 78F4218AY only
4
Data Sheet U14125EJ1V0DS00
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
OVERVIEW OF FUNCTIONS (2/2)
Part Number Item Clock output Buzzer output Watch timer Watchdog timer Standby Interrupt Hardware sources Software sources Non-maskable Maskable
PD78F4216A, PD78F4216AY
2 3 4 5
PD78F4218A, PD78F4218AY
6 7 11 12 13
Selectable from fXX, fXX/2, fXX/2 , fXX/2 , fXX/2 , fXX/2 , fXX/2 , fXX/2 , fXT Selectable from fXX/2 , fXX/2 , fXX/2 , fXX/2 1 channel 1 channel * HALT/STOP/IDLE modes * In low power consumption mode (with subsystem clock): HALT/IDLE modes 29 (internal: 20, external: 9) BRK instruction, BRKCS instruction, operand error Internal: 1, external: 1 Internal: 19, external: 8 * 4 programmable priority levels * 3 service modes: Vectored interrupt/macro service/context switching
10
Supply voltage Package
VDD = 1.9 to 5.5 V 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20)
Data Sheet U14125EJ1V0DS00
5
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
CONTENTS 1. DIFFERENCES AMONG MODELS IN PD784216A/784216AY, 784218A/784218AY SUBSERIES ............................................................................................................................................. 7
2. PIN CONFIGURATION (TOP VIEW) ................................................................................................... 8 3. BLOCK DIAGRAM ............................................................................................................................... 11 4. PIN 4.1 4.2 4.3 FUNCTIONS .................................................................................................................................. 12 Port Pins ..................................................................................................................................... 12 Non-Port Pins ............................................................................................................................. 14 Pin I/O Circuits and Recommended Connections of Unused Pins ....................................... 16
5. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS) ................................................................ 20 6. PROGRAMMING FLASH MEMORY..................................................................................................... 22 6.1 Selecting Communication Mode .............................................................................................. 22 6.2 Flash Memory Programming Function .................................................................................... 23 6.3 Connecting Flashpro ll and Flashpro lll ................................................................................... 24
7. ELECTRICAL SPECIFICATIONS ........................................................................................................ 25 8. PACKAGE DRAWINGS ....................................................................................................................... 47 9. RECOMMENDED SOLDERING CONDITIONS .................................................................................. 49 APPENDIX A. DEVELOPMENT TOOLS ................................................................................................ 50 APPENDIX B. RELATED DOCUMENTS ................................................................................................ 53
6
Data Sheet U14125EJ1V0DS00
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
1. DIFFERENCES AMONG MODELS IN PD784216A/784216AY, 784218A/784218AY SUBSERIES
The only difference among the PD784214A, 784215A, 784216A, 784217A, and 784218A lies in the internal memory capacity. The PD784214AY, 784215AY, 784216AY, 784217AY, and 784218AY are models with the addition of an I2C bus control function. The PD78F4216A, 78F4216AY, 78F4218A, and 78F4218AY are provided with a 128 KB/256 KB flash memory instead of the mask ROM of the above models. These differences are summarized in Table 1-1. Table 1-1. Differences Among Models in PD784216A/784216AY, 784218A/784218AY Subseries
Part Number Item Internal ROM
PD784214A, PD784214AY PD784215A, PD784215AY PD784216A, PD784216AY PD784217A, PD784217AY PD784218A, PD784218AY PD78F4216A, PD78F4216AY PD78F4218A, PD78F4218AY
96 KB (Mask ROM) 3,584 bytes
128 KB (Mask ROM)
192 KB (Mask ROM) 12,800 bytes
256 KB (Mask ROM)
128 KB (Flash memory) 8,192 bytes ProvidedNote
256 KB (Flash memory) 12,800 bytes
Internal RAM
5,120 bytes
8,192 bytes
Internal memory size switching register (IMS) ROM correction
Not provided
Not provided
Provided
Not provided Not provided
Provided
External access status function Supply voltage Electrical specifications Recommended soldering conditions EXA pin
Not provided
Provided
Provided
VDD = 1.8 to 5.5 V Refer to the data sheet for each device.
VDD = 1.9 to 5.5 V
Not provided
Provided
Not provided Not provided Provided
Provided
TEST pin VPP pin
Provided Not provided
Note The internal flash memory capacity and internal RAM capacity can be changed using the internal memory size switching register (IMS). Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing an application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations on the commercial samples (not engineering samples) of the mask ROM version.
Data Sheet U14125EJ1V0DS00
7
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
2. PIN CONFIGURATION (TOP VIEW)
* 100-pin plastic LQFP (fine pitch) (14 x 14)
PD78F4216AGC-8EU, PD78F4218AGC-8EU, PD78F4216AYGC-8EU, PD78F4218AYGC-8EU
P30/TO0 P103/TI8/TO8 P102/TI7/TO7 P101/TI6/TO6 P100/TI5/TO5
P37/EXANote 5 P36/TI01 P35/TI00 P34/TI2 P33/TI1
P67/ASTB P66/WAIT
P32/TO2 P31/TO1
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 P120/RTP0 P121/RTP1 P122/RTP2 P123/RTP3 P124/RTP4 P125/RTP5 P126/RTP6 P127/RTP7 VDD X2 X1 VSS XT2 XT1 RESET P00/INTP0 P01/INTP1 P02/INTP2/NMI P03/INTP3 P04/INTP4 P05/INTP5 P06/INTP6 AVDDNote 2 AVREF0 P10/ANI0 1 75 P62/A18 P61/A17 P60/A16 VSS P57/A15 P56/A14 P55/A13 P54/A12 P53/A11 P52/A10 P51/A9 P50/A8 P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 P42/AD2 P41/AD1 P40/AD0 P87/A7 P86/A6 P85/A5 P84/A4 P83/A3 74 2 73 3 72 4 71 5 70 6 69 7 68 8 67 9 66 10 65 11 64 12 63 13 62 14 61 15 60 16 59 17 58 18 57 19 56 20 55 21 54 22 53 23 52 24 51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P11/ANI1 P12/ANI2 P13/ANI3 P14/ANI4 P15/ANI5 P16/ANI6 P17/ANI7 AVSSNote 3 P130/ANO0 P131/ANO1 AVREF1
P70/RxD2/SI2 P71/TxD2/SO2
P72/ASCK2/SCK2 P20/RxD1/SI1 P21/TxD1/SO1
P22/ASCK1/SCK1 P23/PCL P24/BUZ P25/SI0/SDA0Note 4
P80/A0 P81/A1
Notes 1. Connect the VPP pin to VSS directly or via a pull-down resistor in normal operation mode. Connect the VPP pin to VSS via a pull-down resistor in a system in which the on-chip flash memory is written while mounted on the target board. For the pull-down connection, it is recommended to use a resistor with a resistance ranging from 470 to 10 k. 2. Connect the AVDD pin to VDD. 3. Connect the AVSS pin to VSS. 4. The SCL0 and SDA0 pins are available in the PD78F4216AY, 78F4218AY only. 5. The EXA pin is available in the PD78F4218A, 78F4218AY only.
8
Data Sheet U14125EJ1V0DS00
P26/SO0 P27/SCK0/SCL0Note 4
P82/A2
P65/WR P64/RD P63/A19
P95 P94 P93 P92 P91 P90 VPPNote 1
VDD
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
* 100-pin plastic QFP (14 x 20)
PD78F4216AGF-3BA, PD78F4218AGF-3BA, PD78F4216AYGF-3BA, PD78F4218AYGF-3BA
P55/A13 P54/A12 P53/A11 P52/A10 P51/A9 P50/A8 P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 P42/AD2 P41/AD1 P40/AD0 P87/A7 P86/A6 P85/A5 P57/A15 P56/A14
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 P60/A16 P61/A17 P62/A18 P63/A19 P64/RD P65/WR P66/WAIT P67/ASTB VDD P100/TI5/TO5 P101/TI6/TO6 P102/TI7/TO7 P103/TI8/TO8 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/TI00 P36/TI01 P37/EXANote 5 VPPNote 1 P90 P91 P92 P93 P94 P95 P120/RTP0 P121/RTP1 1 2 3 4 5 6 80 79 78 77 76 75 P84/A4 P83/A3 P82/A2 P81/A1 P80/A0 P27/SCK0/SCL0Note 4 P26/SO0 P25/SI0/SDA0Note 4 P24/BUZ P23/PCL P22/ASCK1/SCK1 P21/TxD1/SO1 P20/RxD1/SI1 P72/ASCK2/SCK2 P71/TxD2/SO2 P70/RxD2/SI2 AVREF1 P131/ANO1 P130/ANO0 AVSSNote 3 P17/ANI7 P16/ANI6 P15/ANI5 P14/ANI4 P13/ANI3 P12/ANI2 P11/ANI1 P10/ANI0 AVREF0 AVDDNote 2
74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VSS
P124/RTP4 P125/RTP5 P126/RTP6 P127/RTP7 VDD
X2 X1 VSS
Notes 1. Connect the VPP pin to VSS directly or via a pull-down resistor in normal operation mode. Connect the VPP pin to VSS via a pull-down resistor in a system in which the on-chip flash memory is written while mounted on the target board. For the pull-down connection, it is recommended to use a resistor with a resistance ranging from 470 to 10 k. 2. Connect the AVDD pin to VDD. 3. Connect the AVSS pin to VSS. 4. The SCL0 and SDA0 pins are available in the PD78F4216AY, 78F4218AY only. 5. The EXA pin is available in the PD78F4218A, 78F4218AY only.
XT2 XT1 RESET P00/INTP0 P01/INTP1 P02/INTP2/NMI P03/INTP3 P04/INTP4 P05/INTP5 P06/INTP6
P122/RTP2 P123/RTP3
Data Sheet U14125EJ1V0DS00
9
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
A0 to A19: AD0 to AD7: ANI0 to ANI7: ANO0, ANO1: ASCK1, ASCK2: ASTB: AVDD: AVREF0, AVREF1: AVSS: BUZ: EXA
Note 2
Address Bus Address/Data Bus Analog Input Analog Output Asynchronous Serial Clock Address Strobe Analog Power Supply Analog Reference Voltage Analog Ground Buzzer Clock
P120 to P127: P130, P131: PCL: RD: RESET: RTP0 to RTP7: RxD1, RxD2: SCK0 to SCK2: SCL0Note 1: SDA0Note 1: SI0 to SI2: SO0 to SO2: TI00, TI01, TI1, TI2, TI5 to TI8: TxD1, TxD2: VDD: VPP: VSS: WAIT: WR: X1, X2: XT1, XT2:
Port 12 Port 13 Programmable Clock Read Strobe Reset Real-time Output Port Receive Data Serial Clock Serial Clock Serial Data Serial Input Serial Output Timer Input Transmit Data Power Supply Programming Power Supply Ground Wait Write Strobe Crystal (Main System Clock) Crystal (Subsystem Clock)
:
External Access Status Output Interrupt from Peripherals Non-maskable Interrupt Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 10
INTP0 to INTP6: NMI: P00 to P06: P10 to P17: P20 to P27: P30 to P37: P40 to P47: P50 to P57: P60 to P67: P70 to P72: P80 to P87: P90 to P95: P100 to P103:
TO0 to TO2, TO5 to TO8: Timer Output
Notes 1. The SCL0 and SDA0 pins are available in the PD78F4216AY, 78F4218AY only. 2. The EXA pin is available in the PD78F4218A, 78F4218AY only.
10
Data Sheet U14125EJ1V0DS00
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
3. BLOCK DIAGRAM
INTP2/NMI INTP0, INTP1, INTP3 to INTP6 TI00 TI01 TO0 TI1 TO1 TI2 TO2
Programmable interrupt controller Timer/event counter (16 bits) Timer/event counter 1 (8 bits) Timer/event counter 2 (8 bits) Timer/event counter 5 (8 bits) Timer/event counter 6 (8 bits) Timer/event counter 7 (8 bits) Timer/event counter 8 (8 bits) Watch timer RAM 78K/IV CPU core
UART/IOE1 Baud-rate generator UART/IOE2 Baud-rate generator Clocked serial interface
RxD1/SI1 TxD1/SO1 ASCK1/SCK1 RxD2/SI2 TxD2/SO2 ASCK2/SCK2 SI0/SDA0Note 1 SO0 SCK0/SCL0Note 1 AD0 to AD7 A0 to A7 A8 to A15
TI5/TO5
Bus I/F
A16 to A19 RD WR WAIT ASTB EXANote 2
TI6/TO6
Flash memory Port 0 Port 1 Port 2 Port 3 Port 4 Port 5
P00 to P06 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P72 P80 to P87 P90 to P95 P100 to P103 P120 to P127 P130, P131 RESET X1
TI7/TO7
TI8/TO8
Watchdog timer
Port 6 Port 7
RTP0 to RTP7 NMI/INTP2 ANO0 ANO1 AVREF1 AVSS P03/INTP3 ANI0 to ANI7 AVREF0 AVDD AVSS PCL
Real-time output port
Port 8 Port 9
D/A converter
Port 10 Port 12 Port 13
A/D converter Clock output control Buzzer output
System control
X2 XT1
BUZ
XT2 VDD VSS VPP
2 Notes 1. This function supports the I C bus interface and is available in the PD78F4216AY, 78F4218AY only.
2. The EXA pin is available in the PD78F4218A, 78F4218AY only.
Data Sheet U14125EJ1V0DS00
11
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
4. PIN FUNCTIONS 4.1 Port Pins (1/2)
Pin Name P00 P01 P02 P03 P04 P05 P06 P10 to P17 Input I/O I/O Alternate Function INTP0 INTP1 INTP2/NMI INTP3 INTP4 INTP5 INTP6 ANI0 to ANI7 Port 1 (P1): * 8-bit input only port Port 2 (P2): * 8-bit I/O port * Input/output can be specified in 1-bit units. * Whether specifying input mode or output mode, an on-chip pull-up resistor can be specified in 1-bit units by means of software. Function Port 0 (P0): * 7-bit I/O port * Input/output can be specified in 1-bit units. * Whether specifying input mode or output mode, an on-chip pull-up resistor can be specified in 1-bit units by means of software.
P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P40 to P47
I/O
RxD1/SI1 TxD1/SO1 ASCK1/SCK1 PCL BUZ SI0/SDA0Note 1 SO0 SCK0/SCL0Note 1
I/O
TO0 TO1 TO2 TI1 TI2 TI00 TI01 EXANote 2
Port 3 (P3): * 8-bit I/O port * Input/output can be specified in 1-bit units. * Whether specifying input mode or output mode, an on-chip pull-up resistor can be specified in 1-bit units by means of software.
I/O
AD0 to AD7
Port 4 (P4): * 8-bit I/O port * Input/output can be specified in 1-bit units. * When used as an input port, an on-chip pull-up resistor can be specified by means of software. * LEDs can be driven directly. Port 5 (P5): * 8-bit I/O port * Input/output can be specified in 1-bit units. * When used as an input port, an on-chip pull-up resistor can be specified by means of software. * LEDs can be driven directly.
P50 to P57
I/O
A8 to A15
Notes 1. 2.
This SDA0 and SCL0 are available in the PD78F4216AY, 78F4218AY only. This function is available in the PD78F4218A, 784218AY only.
12
Data Sheet U14125EJ1V0DS00
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
4.1 Port Pins (2/2)
Pin Name P60 P61 P62 P63 P64 P65 P66 P67 P70 P71 P72 I/O I/O I/O Alternate Function A16 A17 A18 A19 RD WR WAIT ASTB RxD2/SI2 TxD2/SO2 ASCK2/SCK2 Port 7 (P7): * 3-bit I/O port * Input/output can be specified in 1-bit units. * Whether specifying input mode or output mode, an on-chip pull-up resistor can be specified in 1-bit units by means of software. Port 8 (P8): * 8-bit I/O port * Input/output can be specified in 1-bit units. * Whether specifying input mode or output mode, an on-chip pull-up resistor can be specified in 1-bit units by means of software. * The interrupt control flag (KRIF) is set to 1 when a falling edge is detected at a pin of this port. - Port 9 (P9): * N-ch open-drain middle-voltage I/O port * 6-bit I/O port * Input/output can be specified in 1-bit units. * LEDs can be driven directly. Port 10 (P10): * 4-bit I/O port * Input/output can be specified in 1-bit units. * Whether specifying input mode or output mode, an on-chip pull-up resistor can be specified in 1-bit units by means of software. Port 12 (P12): * 8-bit I/O port * Input/output can be specified in 1-bit units. * Whether specifying input mode or output mode, an on-chip pull-up resistor can be specified in 1-bit units by means of software. Port 13 (P13): * 2-bit I/O port * Input/output can be specified in 1-bit units. Function Port 6 (P6): * 8-bit I/O port * Input/output can be specified in 1-bit units. * When used as an input port, an on-chip pull-up resistor can be specified by means of software.
P80 to P87
I/O
A0 to A7
P90 to P95
I/O
P100 P101 P102 P103 P120 to P127
I/O
TI5/TO5 TI6/TO6 TI7/TO7 TI8/TO8
I/O
RTP0 to RTP7
P130, P131
I/O
ANO0, ANO1
Data Sheet U14125EJ1V0DS00
13
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
4.2 Non-Port Pins (1/2)
Pin Name TI00 TI01 TI1 TI2 TI5 TI6 TI7 TI8 TO0 TO1 TO2 TO5 TO6 TO7 TO8 RxD1 RxD2 TxD1 TxD2 ASCK1 ASCK2 SI0 SI1 SI2 SO0 SO1 SO2 SDA0 SCK0 SCK1 SCK2 SCL0 NMI INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6
Note Note
I/O Input
Alternate Function P35 P36 P33 P34 P100/TO5 P101/TO6 P102/TO7 P103/TO8
Function External count clock input to 16-bit timer counter Capture trigger signal input to capture/compare register 00 External count clock input to 8-bit timer counter 1 External count clock input to 8-bit timer counter 2 External count clock input to 8-bit timer counter 5 External count clock input to 8-bit timer counter 6 External count clock input to 8-bit timer counter 7 External count clock input to 8-bit timer counter 8 16-bit timer output (shared by 14-bit PWM output) 8-bit timer output (shared by 8-bit PWM output)
Output
P30 P31 P32 P100/TI5 P101/TI6 P102/TI7 P103/TI8
Input
P20/SI1 P70/SI2
Serial data input (UART1) Serial data input (UART2) Serial data output (UART1) Serial data output (UART2) Baud rate clock input (UART1) Baud rate clock input (UART2) Serial data input (3-wire serial I/O 0) Serial data input (3-wire serial I/O 1) Serial data input (3-wire serial I/O 2) Serial data output (3-wire serial I/O 0) Serial data output (3-wire serial I/O 1) Serial data output (3-wire serial I/O 2) Serial data input/output (I C bus) Serial clock input/output (3-wire serial I/O 0) Serial clock input/output (3-wire serial I/O 1) Serial clock input/output (3-wire serial I/O 2) Serial clock input/output (I C bus) Non-maskable interrupt request input External interrupt request input
2 2
Output
P21/SO1 P71/SO2
Input
P22/SCK1 P72/SCK2
Note
Input
P25/SDA0 P20/RxD1 P70/RxD2
Output
P26 P21/TxD1 P71/TxD2
I/O
P25/SI0 P27/SCL0Note P22/ASCK1 P72/ASCK2 P27/SCK0
Input
P02/INTP2 P00 P01 P02/NMI P03 P04 P05 P06
Note This function is available in the PD78F4216AY, 78F4218AY only.
14
Data Sheet U14125EJ1V0DS00
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
4.2 Non-Port Pins (2/2)
Pin Name PCL BUZ RTP0 to RTP7 AD0 to AD7 A0 to A7 A8 to A15 A16 to A19 RD WR WAIT ASTB EXANote RESET X1 X2 XT1 XT2 ANI0 to ANI7 ANO0, ANO1 AVREF0 AVREF1 AVDD AVSS VDD VSS VPP Input Output Output Input Input - Input - Input Output - P10 to P17 P130, P131 - A/D converter analog input D/A converter analog output A/D converter reference voltage input D/A converter reference voltage input A/D converter positive power supply. Connect to VDD. GND for A/D converter and D/A converter. Connect to VSS. Positive power supply GND Flash memory programming mode setting. Applying high-voltage for program write/verify. Connect this pin to VSS directly or via a pull-down resistor in normal operation mode. Connect the VPP pin to VSS via a pull-down resistor in a system in which the on-chip flash memory is written while mounted on the target board. For the pull-down connection, it is recommended to use a resistor with a resistance ranging from 470 to 10 k. - Connecting crystal resonator for subsystem clock oscillation Output I/O Output Output Output I/O Output Alternate Function P23 P24 P120 to P127 P40 to P47 P80 to P87 P50 to P57 P60 to P63 P64 P65 P66 P67 P37 - - Function Clock output (for trimming main system clock and subsystem clock) Buzzer output Real-time output port that outputs data in synchronization with trigger Lower address/data bus for expanding memory externally Lower address bus for expanding memory externally Middle address bus for expanding memory externally Higher address bus for expanding memory externally Strobe signal output for reading from external memory Strobe signal output for writing to external memory Wait insertion at external memory access Strobe output that externally latches address information output to ports 4 through 6 and 8 to access external memory Status signal output at external memory access System reset input Connecting crystal resonator for main system clock oscillation
Note The EXA pin is available in the PD78F4218A, 78F4218AY only.
Data Sheet U14125EJ1V0DS00
15
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
4.3 Pin I/O Circuits and Recommended Connections of Unused Pins
The I/O circuit type of each pin and recommended connections of unused pins are shown in Table 4-1. For each type of input/output circuit, refer to Figure 4-1. Table 4-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins (1/2)
Pin Name P00/INTP0 P01/INTP1 P02/INTP2/NMI P03/INTP3 to P06/INTP6 P10/ANI0 to P17/ANI7 P20/RxD1/SI1 P21/TxD1/SO1 P22/ASCK1/SCK1 P23/PCL P24/BUZ P25/SI0/SDA0Note 1 P26/SO0 P27/SCK0/SCL0
Note 1
I/O Circuit Type 8-N
I/O I/O
Recommended Connection of Unused Pins Input: Independently connect to VSS via a resistor Output: Leave open
9 10-K 10-L 10-K 10-L
Input I/O
Connect to VSS or VDD Input: Independently connect to VSS via a resistor Output: Leave open
10-K 10-L 10-K 12-E 8-N 10-M 12-E 5-A
P30/TO0 to P32/TO2 P33/TI1, P34/TI2 P35/TI00, P36/TI01 P37/EXA
Note 2
P40/AD0 to P47/AD7 P50/A8 to P57/A15 P60/A16 to P63/A19 P64/RD P65/WR P66/WAIT P67/ASTB P70/RxD2/SI2 P71/TxD2/SO2 P72/ASCK2/SCK2 P80/A0 to P87/A7 P90 to P95 P100/TI5/TO5 P101/TI6/TO6 P102/TI7/TO7 P103/TI8/TO8 P120/RTP0 to P127/RTP7 P130/ANO0, P131/ANO1
8-N 10-M 8-N 12-E 13-D 8-N
12-E 12-F
Notes 1. The SDA0 and SCL0 pins are available in the PD78F4216AY, 78F4218AY only. 2. The EXA pin is available in the PD78F4218A, 78F4218AY only.
16
Data Sheet U14125EJ1V0DS00
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Table 4-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins (2/2)
Pin Name RESET XT1 XT2 AVREF0 AVREF1 AVDD AVSS VPP Connect to VSS Connect this pin to VSS directly or via a pull-down resist in normal operation mode. Connect the VPP pin to VSS via a pull-down resistor in a system in which the on-chip flash memory is written while mounted on the target board. For the pull-down connection, it is recommended to use a resistor with a resistance ranging from 470 to 10 k. - I/O Circuit Type 2-G 16 - I/O Input Connect to VSS Leave open Connect to VSS Connect to VDD Recommended Connection of Unused Pins -
Remark Because the circuit type numbers are standardized among the 78K Series products, they are not sequential in some models (i.e., some circuits are not provided).
Data Sheet U14125EJ1V0DS00
17
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Figure 4-1. Types of Pin I/O Circuits (1/2)
Type 2-G Type 10-K
VDD
Pullup enable IN Data VDD P-ch
P-ch
IN/OUT Open drain Output disable Schmitt-triggered input with hysteresis characteristics N-ch
Type 5-A
VDD
Type 10-L
VDD
Pullup enable VDD Data P-ch
P-ch
Pullup enable VDD Data IN/OUT P-ch
P-ch
IN/OUT Open drain Output disable VSS N-ch
Output disable
N-ch
Input enable Type 8-N VDD Type 10-M VDD
Pullup enable VDD Data P-ch
P-ch
Pullup enable VDD Data IN/OUT P-ch
P-ch
IN/OUT Output disable VSS N-ch
Output disable
N-ch
Type 9
Type 12-E
VDD
IN
P-ch N-ch
Comparator
+ -
Pullup enable VDD Data P-ch
P-ch
VREF (Threshold voltage) Output disable Input enable Input enable P-ch Analog output voltage N-ch
IN/OUT
N-ch
18
Data Sheet U14125EJ1V0DS00
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Figure 4-1. Types of Pin I/O Circuits (2/2)
Type 12-F VDD Data P-ch IN/OUT Output disable Input enable N-ch VSS P-ch N-ch VSS
Type 16 Feedback cut-off P-ch
Analog output voltage
XT1
XT2
Type 13-D IN/OUT Data Output disable N-ch VDD
RD
P-ch
Middle-voltage input buffer
Data Sheet U14125EJ1V0DS00
19
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
5. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS)
IMS is a register that is set by software and is used to specify a part of the internal memory that is not to be used. By setting this register, the internal memory of the PD78F4218AY can be mapped identically to that of a mask ROM version with a different internal memory (ROM and RAM) capacity. IMS is set with an 8-bit memory manipulation instruction. RESET input sets IMS to FFH. (1) PD78F4216A, 78F4216AY Figure 5-1. Internal Memory Size Switching Register (IMS) Format Address: 0FFFCH
7 IMS 1 6 1
After reset: FFH
5 ROM1
W
4 ROM0 3 1 2 1 1 RAM1 0 RAM0
ROM1 0 0 1 1
ROM0 0 1 0 1 48 KB 64 KB 96 KB 128 KB
Internal ROM Capacity Selection
RAM1 0 0 1 1
RAM0 0 1 0 1 3,072 bytes 4,608 bytes 6,114 bytes 7,680 bytes
Peripheral RAM Capacity Selection
Caution IMS is not provided on the mask ROM versions (PD784214A, 784215A, 784216A, PD784214AY, 784215AY, and 784216AY). Table 5-1 shows the IMS setting values to make the memory mapping the same as that of the mask ROM versions. Table 5-1. Setting Value of Internal Memory Size Switching Register (IMS)
Target Mask ROM Version IMS Setting Value ECH FDH FFH
PD784214A, 784214AY PD784215A, 784215AY PD784216A, 784216AY
20
Data Sheet U14125EJ1V0DS00
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
(2) PD78F4218A, 78F4218AY Figure 5-2. Internal Memory Size Switching Register (IMS) Format Address: 0FFFCH
7 IMS 1 6 1
After reset: FFH
5 ROM1
W
4 ROM0 3 1 2 1 1 RAM1 0 RAM0
ROM1 0 0 1 1
ROM0 0 1 0 1 64 KB 128 KB 192 KB 256 KB
Internal ROM Capacity Selection
RAM1 0 0 1 1
RAM0 0 1 0 1 3,072 bytes 6,656 bytes 7,168 bytes 12,288 bytes
Peripheral RAM Capacity Selection
Caution IMS is not provided on the mask ROM versions (PD784217A, 784218A, 784217AY, and 784218AY). Table 5-2 shows the IMS setting values to make the memory mapping the same as that of the mask ROM versions. Table 5-2. Setting Value of Internal Memory Size Switching Register (IMS)
Target Mask ROM Version IMS Setting Value EFH FFH
PD784217A, 784217AY PD784218A, 784218AY
Data Sheet U14125EJ1V0DS00
21
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
6. PROGRAMMING FLASH MEMORY
The flash memory can be written with the PD78F4218AY mounted on the target board (on-board). To do so, connect a dedicated flash programmer (Flashpro II (part number: FL-PR2), Flashpro III (part number: FL-PR3, PGFP3) to the host machine and target system. Writing to flash memory can also be performed using flash memory writing adapter connected to Flashpro II or Flashpro III. Remark FL-PR2 and FL-PR3 are products of Naito Densei Machida Mfg. Co., Ltd.
6.1
Selecting Communication Mode
Select a serial
To write the flash memory, use Flashpro II and Flashpro III by serial communication. selected by the number of VPP pulses shown in Table 6-1. Table 6-1. Communication Modes
Communication Mode 3-wire serial I/O 3 Number of Channels Pins Used
communication mode from those listed in Table 6-1 in the format shown in Figure 6-1. Each communication mode is
Number of VPP Pulses 0
SCK0/P27/SCL0
Note 1
SO0/P26 Note 1 SI0/P25/SDA0 SCK1/ASCK1/P22 SO1/TxD1/P21 SI1/RxD1/P20 SCK2/ASCK2/P72 SO2/TxD2/P71 SI2/RxD2/P70 Handshake
Note 2
1
2
1
SCK0/P27/SCL0
Note 1
3
SO0/P26 Note 1 SI0/P25/SDA0 P24/BUZ UART 2 TxD1/SO1/P21 RxD1/SI1/P20 TxD2/SO2/P71 RxD2/SI2/P70 8
9
Notes 1. The SCL0 and SDA0 pins are available in the PD78F4216AY, 78F4218AY only. 2. This made is available in the PD78F4216A, 78F4216AY (other than I, K, E standard) This made is available in the PD78F4218A, 78F4218AY (other than I standard) Caution Be sure to select a communication mode with the number of VPP pulses shown in Table 6-1.
22
Data Sheet U14125EJ1V0DS00
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Figure 6-1. Communication Mode Selecting Format
VPP pulses 10 V VPP VDD VSS RESET VDD VSS Flash programming mode 1 2 n
6.2
Flash Memory Programming Function
The flash memory is written by transferring or receiving commands and data in a selected communication mode. The major functions of flash memory programming are listed in Table 6-2. Table 6-2. Major Functions of Flash Memory Programming
Function Batch erasure Block erasure Description Erases all contents of memory. Erases contents of specified memory block with one memory block consisting of 16 KB. Checks erased status of entire memory. Checks erased status of specified block. Writes flash memory based on write start address and number of data to be written (in bytes). Compares all contents of memory with input data. Compares contents of specified memory block with input data.
Batch blank check Block blank check Data write
Batch verify Block verify
Data Sheet U14125EJ1V0DS00
23
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
6.3 Connecting Flashpro II and Flashpro III
The Flashpro II, Flashpro III and PD78F4218AY are connected differently depending on the selected communication mode (3-wire serial I/O or UART). communication modes. Figure 6-2. Connection of Flashpro II and Flashpro III in 3-Wire Serial I/O Mode Figures 6-2 to 6-4 show the connections in the respective
VPP VDD RESET Flashpro ll, Flashpro lll SCK0 or SCK1 or SCK2 SI0 or SI1 or SI2 SO0 or SO1 or SO2 VSS
PD78F4218AY
Figure 6-3. Connection of Flashpro III in Handshake Mode
VPP VDD RESET SCK0 Flashpro lll SI0 SO0 P24 VSS
PD78F4218AY
Figure 6-4. Connection of Flashpro II and Flashpro III in UART Mode
VPP VDD RESET Flashpro ll, Flashpro lll RxD1 or RxD2 TxD1 or TxD2 VSS
PD78F4218AY
24
Data Sheet U14125EJ1V0DS00
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
7. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25C)
Parameter Supply voltage Symbol VDD AVDD AVSS AVREF0 AVREF1 Input voltage VI1 VI2 VI3 Analog input voltage Output voltage Output current, low VAN VO IOL Per pin Total of P2, P4 to P8 Total of P0, P3, P9, P10, P12, P13 Total of all pins Output current, high IOH Per pin Total of all pins Operating ambient temperature Storage temperature TA A/D converter reference voltage input D/A converter reference voltage input Other than P90 to P95 P90 to P95 VPP pin for programming Analog input pin N-ch open drain Conditions Ratings -0.3 to +6.5 -0.3 to VDD + 0.3 -0.3 to VSS + 0.3 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to +12 -0.3 to +10.5 AVSS - 0.3 to AVREF0 + 0.3 -0.3 to VDD + 0.3 15 75 75 100 -10 -50 -40 to +85 -65 to +125 Unit V V V V V V V V V V mA mA mA mA mA mA C C
Tstg
Caution
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
Data Sheet U14125EJ1V0DS00
25
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Operating Conditions
* Operating ambient temperature (TA): -40 to +85C * Supply voltage and clock cycle time: See Figure 7-1 * Operating voltage with subsystem clock operation: VDD = 1.9 to 5.5 V Figure 7-1. Supply Voltage and Clock Cycle Time (CPU Clock Frequency: fCPU)
10,000
8,000
500
Clock cycle time tCYK [ns]
400 Guaranteed operating range
320 300
200 160 100 80
0 0 1 1.9 2 2.7 3 Supply voltage [V] 4 4.5 5 5.5 6
Capacitance (TA = 25C, VDD = VSS = 0 V)
Parameter Input capacitance Symbol CI f = 1 MHz Unmeasured pins returned to 0 V. Conditions Other than Port 9 Port 9 Other than Port 9 Port 9 I/O capacitance CIO Other than Port 9 Port 9 MIN. TYP. MAX. 15 20 15 20 15 20 Unit pF pF pF pF pF pF
Output capacitance
CO
26
Data Sheet U14125EJ1V0DS00
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Main System Clock Oscillator Characteristics (TA = -40 to +85C)
Resonator Ceramic resonator or crystal resonator Recommended Circuit
X2 X1 VSS
Parameter Oscillation frequency (fX)
Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 1.9 V VDD < 2.0 V
MIN. 2 2 2 2
TYP.
MAX. 12.5 6.25 3.125 2
Unit MHz
External clock
X1 input frequency (fX)
4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V
2 2 2 2 15
12.5 6.25 3.125 2 250
MHz
X2
X1
1.9 V VDD < 2.0 V X1 input high-/lowlevel width (tWXH, tWXL) X1 input rising/falling time (tXR, tXF) 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 1.9 V VDD < 2.0 V
ns
PD74HCU04
0 0 0 0
5 10 20 30
ns
Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched back to the main system clock after the oscillation stabilization time is secured by the program. Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
Data Sheet U14125EJ1V0DS00
27
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Subsystem Clock Oscillator Characteristics (TA = -40 to +85C)
Resonator Crystal resonator Recommended Circuit
VSS XT2 XT1
Parameter Oscillation frequency (fXT) Oscillation stabilization timeNote
Conditions
MIN. 32
TYP. 32.768
MAX. 35
Unit kHz
4.5 V VDD 5.5 V 1.9 V VDD < 4.5 V
1.2
2 10
s
External clock
XT2
XT1
XT1 input frequency (fXT) XT1 input high-/lowlevel width (tXTH, tXTL)
32
35
kHz
PD74HCU04
14.3
15.6
s
Note Time required to stabilize oscillation after applying supply voltage (VDD). Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
28
Data Sheet U14125EJ1V0DS00
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
DC Characteristics (TA = -40 to +85C, VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V) (1/3)
Parameter Input voltage, low Symbol VIL1 Note 1 Conditions 2.2 V VDD 5.5 V 1.9 V VDD < 2.2 V VIL2 P00 to P06, P20, P22, P33, 2.2 V VDD 5.5 V P34, P70, P72, 1.9 V VDD < 2.2 V P100 to P103, RESET P90 to P95 (N-ch open drain) P10 to P17, P130, P131 2.2 V VDD 5.5 V 1.9 V VDD < 2.2 V 2.2 V VDD 5.5 V 1.9 V VDD < 2.2 V VIL5 X1, X2, XT1, XT2 2.2 V VDD 5.5 V 1.9 V VDD < 2.2 V VIL6 P25, P27 2.2 V VDD 5.5 V 1.9 V VDD < 2.2 V Input voltage, high VIH1 Note 1 2.2 V VDD 5.5 V 1.9 V VDD < 2.2 V VIH2 P00 to P06, P20, P22, P33, 2.2 V VDD 5.5 V P34, P70, P72, 1.9 V VDD < 2.2 V P100 to P103, RESET P90 to P95 (N-ch open drain) P10 to P17, P130, P131 2.2 V VDD 5.5 V 1.9 V VDD < 2.2 V 2.2 V VDD 5.5 V 1.9 V VDD < 2.2 V VIH5 X1, X2, XT1, XT2 2.2 V VDD 5.5 V 1.9 V VDD < 2.2 V VIH6 P25, P27 2.2 V VDD 5.5 V 1.9 V VDD < 2.2 V Output voltage, low VOL1 For pins other than P40 to P47, P50 to P57, Note 1 P90 to P95 IOL = 1.6 mA P40 to P47, P50 to P57 Note 2 IOL = 8 mA P90 to P95 IOL = 15 mA VOL2 Output voltage, high VOH1 IOL = 400 A IOH = -1 mA VIN = 0 V
Note 2 Note 2 Note 2
MIN. 0 0 0 0 0 0 0 0 0 0 0 0 0.7VDD 0.8VDD 0.8VDD 0.85VDD 0.7VDD 0.8VDD 0.7VDD 0.8VDD 0.8VDD 0.85VDD 0.7VDD 0.8VDD
TYP.
MAX. 0.3VDD 0.2VDD 0.2VDD 0.15VDD 0.3VDD 0.2VDD 0.3VDD 0.2VDD 0.2VDD 0.1VDD 0.3VDD 0.2VDD VDD VDD VDD VDD 12 VDD VDD VDD VDD VDD VDD VDD 0.4
Unit V
V
VIL3
V
VIL4
V
V
V
V
V
VIH3
V
VIH4
V
V
V
4.5 V VDD 5.5 V
V
4.5 V VDD 5.5 V 4.5 V VDD 5.5 V 4.5 V VDD 5.5 V VDD - 1.0 VDD - 0.5 Except X1, X2, XT1, XT2 X1, X2, XT1, XT2 0.8
1.0 2.0 0.5
V V V V V
IOL = -100 A Input leakage current, low ILIL1 ILIL2 Input leakage current, high ILIH1 ILIH2 ILIH3 Output leakage current, low Output leakage current, high ILOL1 ILOH1 VIN = VDD
Note 2
-3 -20 3 20 20 -3 3
A A A A A A A
Except X1, X2, XT1, XT2 X1, X2, XT1, XT2
VIN = 12 V (N-ch open drain) P90 to P95 VOUT = 0 V VOUT = VDD
Notes 1. P21, P23, P24, P26, P30 to P32, P35 to P37, P40 to P47, P50 to P57, P60 to P67, P71, P80 to P87, P120 to P127 2. Per pin
Data Sheet U14125EJ1V0DS00
29
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
DC Characteristics (TA = -40 to +85C, VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V) (2/3)
(1) PD78F4216A, 78F4216AY
Parameter Supply voltage Symbol IDD1 Operation mode Conditions fXX = 12.5 MHz, VDD = 5.0 V 10% fXX = 6 MHz, VDD = 3.0 V 10% fXX = 2 MHz, VDD = 2.0 V 5% IDD2 HALT mode fXX = 12.5 MHz, VDD = 5.0 V 10% fXX = 6 MHz, VDD = 3.0 V 10% fXX = 2 MHz, VDD = 2.0 V 5% IDD3 IDLE mode fXX = 12.5 MHz, VDD = 5.0 V 10% fXX = 6 MHz, VDD = 3.0 V 10% fXX = 2 MHz, VDD = 2.0 V 5% IDD4 Operation modeNote fXX = 32 kHz, VDD = 5.0 V 10% fXX = 32 kHz, VDD = 3.0 V 10% fXX = 32 kHz, 2.0 V VDD 2.7 V fXX = 32 kHz, 1.9 V VDD < 2.0 V IDD5 HALT modeNote fXX = 32 kHz, VDD = 5.0 V 10% fXX = 32 kHz, VDD = 3.0 V 10% fXX = 32 kHz, 2.0 V VDD 2.7 V fXX = 32 kHz, 1.9 V VDD < 2.0 V IDD6 IDLE modeNote fXX = 32 kHz, VDD = 5.0 V 10% fXX = 32 kHz, VDD = 3.0 V 10% fXX = 32 kHz, 2.0 V VDD 2.7 V fXX = 32 kHz, 1.9 V VDD < 2.0 V Data retention voltage Data retention current VDDDR IDDDR HALT, IDLE modes STOP mode VDD = 2.0 V 5% VDD = 5.0 V 10% Pull-up resistor RL VIN = 0 V 10 1.9 2 10 30 MIN. TYP. 17 5 2 6 2 0.4 1 0.5 0.3 130 90 80 70 60 20 15 10 50 15 12 7 MAX. 40 17 10 20 10 7 3 1.3 0.9 500 350 300 250 200 160 120 100 190 150 110 90 5.5 10 50 100 Unit mA mA mA mA mA mA mA mA mA
A A A A A A A A A A A A
V
A A
k
Note When main system clock is stopped and subsystem clock is operating. Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
30
Data Sheet U14125EJ1V0DS00
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
DC Characteristics (TA = -40 to +85C, VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V) (3/3)
(2) PD78F4218A, 78F4218AY
Parameter Supply voltage Symbol IDD1 Operation mode Conditions fXX = 12.5 MHz, VDD = 5.0 V 10% fXX = 6 MHz, VDD = 3.0 V 10% fXX = 3 MHz, VDD = 2.0 V 5% IDD2 HALT mode fXX = 12.5 MHz, VDD = 5.0 V 10% fXX = 6 MHz, VDD = 3.0 V 10% fXX = 3 MHz, VDD = 2.0 V 5% IDD3 IDLE mode fXX = 12.5 MHz, VDD = 5.0 V 10% fXX = 6 MHz, VDD = 3.0 V 10% fXX = 3 MHz, VDD = 2.0 V 5% IDD4 Operation modeNote fXX = 32 kHz, VDD = 5.0 V 10% fXX = 32 kHz, VDD = 3.0 V 10% fXX = 32 kHz, 2.0 V VDD 2.7 V fXX = 32 kHz, 1.9 V VDD < 2.0 V IDD5 HALT modeNote fXX = 32 kHz, VDD = 5.0 V 10% fXX = 32 kHz, VDD = 3.0 V 10% fXX = 32 kHz, 2.0 V VDD 2.7 V fXX = 32 kHz, 1.9 V VDD < 2.0 V IDD6 IDLE modeNote fXX = 32 kHz, VDD = 5.0 V 10% fXX = 32 kHz, VDD = 3.0 V 10% fXX = 32 kHz, 2.0 V VDD 2.7 V fXX = 32 kHz, 1.9 V VDD < 2.0 V Data retention voltage Data retention current VDDDR IDDDR HALT, IDLE modes STOP mode VDD = 2.0 V 5% VDD = 5.0 V 10% Pull-up resistor RL VIN = 0 V 10 1.9 2 10 30 MIN. TYP. 19 6 2 7 2 0.5 1 0.5 0.3 140 100 90 80 60 20 15 10 50 15 12 7 MAX. 40 17 10 20 10 7 3 1.3 0.9 500 350 300 250 200 160 120 100 190 150 110 90 5.5 10 50 100 Unit mA mA mA mA mA mA mA mA mA
A A A A A A A A A A A A
V
A A
k
Note When main system clock is stopped and subsystem clock is operating. Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
Data Sheet U14125EJ1V0DS00
31
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
AC Characteristics (TA = -40 to +85C, VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V)
(1) Read/write operation (1/2)
Parameter Cycle time Symbol tCYK Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 1.9 V VDD < 2.0 V Address setup time (to ASTB) tSAST VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 5% Address hold time (from ASTB) tHSTLA VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 5% ASTB high-level width tWSTH VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 5% Address hold time (from RD) tHRA VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 5% Delay time from address to RD tDAR VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 5% Address float time (from RD) tFAR VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 5% Data input time from address tDAID VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 5% Data input time from ASTB tDSTID VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 5% Data input time from RD tDRID VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 5% Delay time from ASTB to RD tDSTR VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 5% Data hold time (from RD) tHRID VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 5% 0.5T - 9 0.5T - 9 0.5T - 20 0 0 0 MIN. 80 160 320 500 (0.5 + a)T - 20 (0.5 + a)T - 40 (0.5 + a)T - 80 0.5T - 19 0.5T - 24 0.5T - 34 (0.5 + a)T - 17 (0.5 + a)T - 40 (0.5 + a)T - 110 0.5T - 14 0.5T - 14 0.5T - 14 (1 + a)T - 24 (1 + a)T - 35 (1 + a)T - 80 0 0 0 (2.5 + a + n)T - 37 (2.5 + a + n)T - 52 (2.5 + a + n)T - 120 (2 + n)T - 35 (2 + n)T - 50 (2 + n)T - 80 (1.5 + n)T - 40 (1.5 + n)T - 50 (1.5 + n)T - 90 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remark T: tCYK = 1/fXX (fXX: main system clock frequency) a: 1 (during address wait), otherwise, 0 n: Number of waits (n 0)
32
Data Sheet U14125EJ1V0DS00
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
AC Characteristics
(1) Read/write operation (2/2)
Parameter Address active time from RD Symbol tDRA Conditions VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 5% Delay time from RD to ASTB tDRST VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 5% RD low-level width tWRL VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 5% Delay time from address to WR tDAW VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 5% Address hold time (from WR) tHRD VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 5% Delay time from ASTB to data tDSTOD output VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 5% Delay time from WR to data tDWOD output VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 5% Delay time from ASTB to WR tDSTW VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 5% Data setup time (to WR) tSODWR VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 5% Data hold time (from WR) tHWOD VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 5% Delay time from WR to ASTB tDWST VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 5% WR low-level width tWWL VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 5% 0.5T - 9 0.5T - 9 0.5T - 20 (1.5 + n)T - 20 (1.5 + n)T - 25 (1.5 + n)T - 70 0.5T - 14 0.5T - 14 0.5T - 50 0.5T - 9 0.5T - 9 0.5T - 30 (1.5 + n)T - 25 (1.5 + n)T - 30 (1.5 + n)T - 30 MIN. 0.5T - 2 0.5T - 12 0.5T - 35 0.5T - 9 0.5T - 9 0.5T - 40 (1.5 + n)T - 25 (1.5 + n)T - 30 (1.5 + n)T - 25 (1 + a)T - 24 (1 + a)T - 34 (1 + a)T - 70 0.5T - 14 0.5T - 14 0.5T - 14 0.5T + 15 0.5T + 30 0.5T + 240 0.5T - 30 0.5T - 30 0.5T - 30 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remark T: tCYK = 1/fXX (fXX: main system clock frequency) a: 1 (during address wait), otherwise, 0 n: Number of wait states (n 0)
Data Sheet U14125EJ1V0DS00
33
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
AC Characteristics
(2) External wait timing
Parameter Input time from address to WAIT Symbol tDAWT Conditions VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 5% Input time from ASTB to WAIT tDSTWT VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 5% Hold time from ASTB to WAIT tHSTWT VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 5% Delay time from ASTB to WAIT tDRWTL tDSTWTH VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 5% Input time from RD to WAIT VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 5% Hold time from RD to WAIT tHRWT VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 5% Delay time from RD to WAIT tDRWTH VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 5% Data input time from WAIT tDWTID VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 5% Delay time from WAIT to RD tDWTR VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 5% Delay time from WAIT to WR tDWTW VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 5% Input time from WR to WAIT tDWWTL VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 5% Hold time from WR to WAIT tHWWT VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 5% Delay time from WR to WAIT tDWWTH VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 5% nT + 5 nT + 10 nT + 30 (1 + n)T - 40 (1 + n)T - 60 (1 + n)T - 90 0.5T 0.5T 0.5T + 5 0.5T 0.5T 0.5T + 5 T - 40 T - 60 T - 90 nT + 5 nT + 10 nT + 30 (1 + n)T - 40 (1 + n)T - 60 (1 + n)T - 90 0.5T - 5 0.5T - 10 0.5T - 30 (0.5 + n)T + 5 (0.5 + n)T + 10 (0.5 + n)T + 30 (1.5 + n)T - 40 (1.5 + n)T - 60 (1.5 + n)T - 90 T - 40 T - 60 T - 70 MIN. TYP. MAX. (2 + a)T - 40 (2 + a)T - 60 (2 + a)T - 300 1.5T - 40 1.5T - 60 1.5T - 260 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remark T: tCYK = 1/fXX (fXX: main system clock frequency) a: 1 (during address wait), otherwise, 0 n: Number of wait states (n 0)
34
Data Sheet U14125EJ1V0DS00
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Serial Operation (TA = -40 to +85C, VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V)
(a) 3-wire serial I/O mode (SCK: Internal clock output)
Parameter SCK cycle time Symbol tKCY1 2.7 V VDD 5.5 V 2.7 V VDD 5.5 V 2.7 V VDD 5.5 V Conditions MIN. 800 3,200 SCK high-/low-level width tKH1, tKL1 tSIK1 350 1,500 10 30 SI hold time (from SCK) SO output delay time (from SCK) tKSI1 tKSO1 40 30 TYP. MAX. Unit ns ns ns ns ns ns ns ns
SI setup time (to SCK)
(b) 3-wire serial I/O mode (SCK: External clock input)
Parameter SCK cycle time Symbol tKCY2 2.7 V VDD 5.5 V 2.7 V VDD 5.5 V 2.7 V VDD 5.5 V Conditions MIN. 800 3,200 SCK high-/low-level width tKH2 tKL2 tSIK2 400 1,600 10 30 SI hold time (from SCK) SO output delay time (from SCK) tKSI2 tKSO2 40 30 TYP. MAX. Unit ns ns ns ns ns ns ns ns
SI setup time (to SCK)
(c) UART mode
Parameter ASCK cycle time Symbol tKCY3 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V Conditions MIN. 417 833 1,667 ASCK high-/low-level width tKH3 tKL3 208 416 833 TYP. MAX. Unit ns ns ns ns ns ns
Data Sheet U14125EJ1V0DS00
35
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
(d) I2C bus mode
Parameter
Symbol MIN.
Standard Mode MAX. 100 - - - - - - - - 1,000
High-Speed Mode MIN. 0 1.3 MAX. 400 - - - - - - 0.9Note 3 - 300
Unit
SCL0 clock frequency Bus free time (between stop and start conditions) Hold timeNote1 Low-level width of SCL0 clock High-level width of SCL0 clock Setup time of start/restart conditions Data hold When using CBUStime compatible master When using I C bus Data setup time Rise time of SDA0 and SCL0 signals Fall time of SDA0 and SCL0 signals Setup time of stop condition Pulse width of spike restricted by input filter Load capacitance of each bus line
2
fCLK tBUF
0 4.7
kHz
s s s s s s s
ns ns
tHD : STA tLOW tHIGH tSU : STA
4.0 4.7 4.0 4.7
0.6 1.3 0.6 0.6 - 0Note 2 100
Note 4 Note 5
tHD : DAT
5.0 0Note 2
tSU : DAT tR
250 - -
20 + 0.1Cb
tF
300 - -
20 + 0.1CbNote 5
300 - 50
ns
tSU : STO tSP
4.0 - -
0.6 0 -
s
ns
Cb
400
400
pF
Notes 1. For the start condition, the first clock pulse is generated after the hold time. 2. To fill the undefined area of the SCL0 falling edge, it is necessary for the device to provide an internal SDA0 signal (on VIHmin.) with at least 300 ns of hold time. 3. If the device does not extend the SCL0 signal low-level hold time (tLOW), only the maximum data hold time tHD : DAT needs to be satisfied. 4. The high-speed mode I2C bus can be used in a standard mode I2C bus system. In this case, the conditions described below must be satisfied. * If the device does not extend the SCL0 signal low-level hold time tSU : DAT 250 ns * If the device extends the SCL0 signal low-level hold time Be sure to transmit the data bit to the SDA0 line before the SCL0 line is released (tRmax. + tSU : = 1,000 + 250 = 1,250 ns by standard mode I C bus specification) 5. Cb: Total capacitance per bus line (unit: pF)
2 DAT
36
Data Sheet U14125EJ1V0DS00
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Other Operations (TA = -40 to +85C, VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V)
Parameter NMI high-/low-level width Symbol tWNIL tWNIH tWITL tWITH tWRSL tWRSH INTP0 to INTP6 Conditions MIN. 10 TYP. MAX. Unit
s
ns
Interrupt input high-/low-level width
100
RESET high-/low-level width
10
s
Clock Output Operation (TA = -40 to +85C, VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V)
Parameter PCL cycle time PCL high-/low-level width Symbol tCYCL tCLL tCLH tCLR tCLF Conditions 4.5 V VDD 5.5 V, nT 4.5 V VDD 5.5 V, 0.5T - 10 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 1.9 V VDD < 2.7 V MIN. 80 30 TYP. MAX. 31,250 15,615 Unit ns ns
PCL rise/fall time
5 10 20
ns ns ns
Remark T: tCYK = 1/fXX (fXX: Main system clock frequency) n: Divided frequency ratio set by software in the CPU * When using the main system clock: n = 1, 2, 4, 8, 16, 32, 64, 128 * When using the subsystem clock: n = 1
Data Sheet U14125EJ1V0DS00
37
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
A/D Converter Characteristics (TA = -40 to +85C, VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V)
Parameter Resolution Overall error
Notes 1, 2
Symbol
Conditions
MIN. 8
TYP. 8
MAX. 8 1.2 1.6
Unit bits %FSR
2.7 V VDD 5.5 V 2.2 V AVREF0 VDD 1.9 V VDD < 2.7 V 1.9 V AVREF0 VDD
%FSR
Conversion time Sampling time Analog input voltage Reference voltage Resistance between AVREF0 and AVSS
tCONV tSAMP VIAN AVREF0 RAVREF0 When not A/D converting
14 24/fXX AVSS 1.9 40
144
s s
AVREF0 AVDD
V V k
Notes 1. Quantization error (1/2 LSB) is not included. 2. Overall error is indicated as a ratio to the full-scale value. Remark fXX : Main system clock frequency
D/A Converter Characteristics (TA = -40 to +85C, VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V)
Parameter Resolution Overall error
Notes 1, 2
Symbol
Conditions
MIN. 8
TYP. 8
MAX. 8 0.6 1.2
Unit Bits %FSR
R = 10 M, 2.0 V AVREF1 VDD, 2.0 V VDD 5.5 V R = 10 M, 1.9 V AVREF1 VDD, 1.9 V VDD 2.0 V
%FSR
Settling time
Load conditions: C = 30 pF
4.5 V AVREF1 5.5 V 2.7 V AVREF1 < 4.5 V 1.9 V AVREF1 < 2.7 V
10 15 20 8 1.9 VDD 2.5
s s s
k V mA
Output resistance Reference voltage AVREF1 current
RO AVREF1 AIREF1
DACS0, 1 = 55H
For only 1 channel
Notes 1. Quantization error (1/2 LSB) is not included. 2. Overall error is indicated as a ratio to the full-scale value.
38
Data Sheet U14125EJ1V0DS00
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Data Retention Characteristics (TA = -40 to +85C, VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V)
Parameter Data retention voltage Data retention current Symbol VDDDR IDDDR STOP mode VDDDR = 5.0 V 10% VDDDR = 2.0 V 5% VDD rise time VDD fall time VDD hold time (from STOP mode setting) STOP release signal input time Oscillation stabilization wait time tRVD tFVD tHVD 200 200 0 Conditions MIN. 1.9 10 2 TYP. MAX. 5.5 50 10 Unit V
A A s s
ms
tDREL tWAIT Crystal resonator Ceramic resonator
0 30 5 0 0.9VDDDR 0.1VDDDR VDDDR
ms ms ms V V
Low-level input voltage High-level input voltage
VIL VIH
RESET, P00/INTP0 to P06/INTP6
AC Timing Test Points
VDD - 1 V
0.8VDD or 1.9 V Test points 0.8 V
0.8VDD or 1.9 V 0.8 V
0.45 V
Data Sheet U14125EJ1V0DS00
39
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Timing Waveforms
(1) Read operations
(CLK) tCYK
A0 to A7 (Output)
Lower address
Lower address
A8 to A19 (Output) tDAID
Higher address tHRA tDRA Hi-Z Data (Input) tHRID tFAR Hi-Z
Higher address
tDSTID AD0 to AD7 (I/O) Hi-Z Lower address (Output) tSAST ASTB (Output) tHSTLA
Lower address (Output)
tWSTH tDSTR tDAR tDRID tWRL tDRWTL tDAWT tDRWTH tHRWT tDWTR tDWTID tDRST
RD (Output)
WAIT (Input) tDSTWT tDSTWTH tHSTWT
Remark The signal is output from pins A0 to A7 when P80 to P87 are unused.
40
Data Sheet U14125EJ1V0DS00
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
(2) Write operation
(CLK) tCYK
A0 to A7 (Output)
Lower address
Lower address
A8 to A19 (Output) tDAID
Higher address tHWA tDAW Hi-Z Data (Output) tHWOD tFAR tSODWR Hi-Z
Higher address
tDSTOD AD0 to AD7 (Output) Hi-Z Lower address (Output) tSAST ASTB (Output) tHSTLA
Lower address (Output)
tWSTH tDSTW tDAW tDWOD tWWL tDWWTL tDAWT tDWWTH tHWWT tDWTW tDWTID tDWST
WR (Output)
WAIT (Input) tDSTWT tDSTWTH tHSTWT
Remark The signal is output from pins A0 to A7 when P80 to P87 are unused.
Data Sheet U14125EJ1V0DS00
41
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Serial Operation
(1) 3-wire serial I/O mode
tKCY1, 2 tKH1, 2 tKL1, 2 SCK tKSO1, 2 tKSI1, 2 tSIK1, 2 SI/SO
(2) UART mode
tKCY3 tKH3 ASCK tKL3
(3) I2C bus mode (PD78F4216AY, 78F4218AY only)
tR SCL0 tHD : DAT tHD : STA tF
tHIGH tSU : DAT
tSU : STA
tHD : STA
tSP
tSU : STO
SDA0 tBUF Stop condition Start condition Restart condition Stop condition
42
Data Sheet U14125EJ1V0DS00
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Clock Output Timing
tCLH tCLL
CLKOUT tCLR tCYCL tCLF
Interrupt Input Timing
tWNIH tWNIL
NMI
tWITH
tWITL
INTP0 to INTP6
Reset Input Timing
tWRSH
tWRSL
RESET
Data Sheet U14125EJ1V0DS00
43
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Clock Timing
tWXH tWXL
X1 tXR 1/fX tXF
tXTH
tXTL
XT1
1/fXT
Data Retention Characteristics
STOP mode setting
VDD tHVD tFVD
VDDDR tRVD tDREL tWAIT
RESET
NMI (Cleared by falling edge)
NMI (Cleared by rising edge)
44
Data Sheet U14125EJ1V0DS00
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Flash Memory Programming Characteristics (VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V, VPP = 9.7 to 10.3 V)
(1) Basic characteristics
Parameter Operating frequency Symbol fX Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 1.9 V VDD < 2.0 V Supply voltage
Note 1
MIN. 2 2 2 2 1.9
TYP.
MAX. 12.5 6.25 3.125
Unit MHz MHz MHz MHz V V V V mA mA Times
2
2 5.5 0.2VDD
VDD VPPL VPP VPPH Upon VPP low-level detection Upon VPP high-level detection Upon VPP high-voltage detection
0 0.9VDD 9.7 VDD 10
1.1VDD 10.3 40
VDD supply current VPP supply current Write count Operating temperature Storage temperature
Note 3
IDD IPP CWRT TA Tstg TPRG VPP = 10 V 20
Note2
100
-40 -65 10
85 125 40
C C C
Note 4
Programming temperature
Notes 1. PD78F4216A, 78F4216AY
K standard: 2.7 V VDD < 5.5 V, VPP = 10.3 0.3 V E standard: 2.7 V VDD < 5.5 V, VPP = 10.0 0.3 V
2. Operation cannot be guaranteed when the number of writes exceeds 20 times. In the case of the
PD78F4216A and 78F4216AY with K standard, operation cannot be guaranteed when the number of
writes exceeds 5 times. 3. PD78F4216A, 78F4216AY K standard: TA = -10 to +60C 4. PD78F4216A, 78F4216AY K standard: TA = -10 to +80C Cautions 1. If writing is not successful in write operation, execute the program command again, and execute the verify command to confirm the normal completion of the write operation. (PD78F4216A, 78F4216AY: I, K, E, P standard) 2. Handshake mode is supported by the following products.
PD78F4216A, 78F4216AY: Other than I, K, E standard PD78F4218A, 78F4218AY: Other than I standard
Remark The fifth alphabetic character from the left in the lot number indicates the standard of the product. After executing the program command, execute the verify command to confirm the normal completion of the write operation. Handshake mode is the CSI write mode that uses P24.
Data Sheet U14125EJ1V0DS00
45
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Flash Memory Programming Characteristics (VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V, VPP = 9.7 to 10.3 V)
(2) Serial write operation characteristics
Parameter VPP setup time VPP setup time to VDD RESET set up time to VPP VPP count start time from RESET Count execution time VPP counter high-level width VPP counter low-level width VPP counter noise elimination width Symbol tPSRON tDRPSR tPSRRF tRFCF tCOUNT tCH tCL tNFW 8.0 8.0 40 Conditions VPP high voltage VPP high voltage VPP high voltage MIN. 1.0 10 1.0 1.0 1.0 TYP. MAX. Unit
s s s s
ms
s s
ns
Flash Memory Write Mode Setting Timing
VDD VDD 0V VPPH VPP VPP VPPL tPSRON tPSRRF tCOUNT VDD RESET (input) 0V tCL tDRPSR tRFCF tCH
46
Data Sheet U14125EJ1V0DS00
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
8. PACKAGE DRAWINGS
100-PIN PLASTIC LQFP (FINE PITCH) (14x14)
A B
75 76
51 50
detail of lead end S CD Q R
100 1
26 25
F G P H I
M
J K S
N
S L M
NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 16.000.20 14.000.20 14.000.20 16.000.20 1.00 1.00 0.22 +0.05 -0.04 0.08 0.50 (T.P.) 1.000.20 0.500.20 0.17 +0.03 -0.07 0.08 1.400.05 0.100.05 3 +7 -3 1.60 MAX.
S100GC-50-8EU, 8EA-2
Remark The external dimensions and material of the ES version are the same as those of the mass-produced version.
Data Sheet U14125EJ1V0DS00
47
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
100-PIN PLASTIC QFP (14x20)
A B
80 81
51 50
detail of lead end S CD Q R
100 1
31 30
F G H I
M
J
P
K S N S L M
NOTE Each lead centerline is located within 0.15 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 23.60.4 20.00.2 14.00.2 17.60.4 0.8 0.6 0.300.10 0.15 0.65 (T.P.) 1.80.2 0.80.2 0.15+0.10 -0.05 0.10 2.70.1 0.10.1 55 3.0 MAX.
P100GF-65-3BA1-4
Remark The external dimensions and material of the ES version are the same as those of the mass-produced version.
48
Data Sheet U14125EJ1V0DS00
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
9. RECOMMENDED SOLDERING CONDITIONS
The PD78F4218AY should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 9-1. Surface Mounting Type Soldering Conditions
(1) PD78F4216AGC-8EU:100-pin plastic LQFP (fine pitch) (14 x 14)
PD78F4218AGC-8EU:100-pin plastic LQFP (fine pitch) (14 x 14) PD78F4216AYGC-8EU:100-pin plastic LQFP (fine pitch) (14 x 14) PD78F4218AYGC-8EU: 100-pin plastic LQFP (fine pitch) (14 x 14)
Soldering Method Soldering Conditions Recommended Condition Symbol IR35-107-2
Infrared reflow
Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Note Count: Two times or less, Exposure limit: 7 days (after that, prebake at 125C for 10 hours)
VPS
Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Note Count: Two times or less, Exposure limit: 7 days (after that, prebake at 125C for 10 hours)
VP15-107-2
Partial heating
Pin temperature: 300C max., Time: 3 seconds max. (per pin row)
-
Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating).
(2) PD78F4216AGF-3BA:100-pin plastic QFP (14 x 20)
PD78F4218AGF-3BA:100-pin plastic QFP (14 x 20) PD78F4216AYGF-3BA:100-pin plastic QFP (14 x 20) PD78F4218AYGF-3BA: 100-pin plastic QFP (14 x 20)
Soldering Method Soldering Conditions Recommended Condition Symbol IR35-00-2
Infrared reflow
Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Two times or less Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Two times or less Solder bath temperature: 260C max., Time: 10 seconds max., Count: Once, Preheating temperature: 120C max. (package surface temperature) Pin temperature: 300C max., Time: 3 seconds max. (per pin row)
VPS
VP15-00-2
Wave soldering
WS60-00-1 -
Partial heating
Caution
Do not use different soldering methods together (except for partial heating).
Data Sheet U14125EJ1V0DS00
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PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the PD78F4218AY. Also refer to (5) Cautions on using development tools. (1) Language processing software
RA78K4 CC78K4 DF784218 CC78K4-L Assembler package common to 78K/IV Series C compiler package common to 78K/IV Series Device file common to PD784216A, 784216AY, 784218A, 784218AY Subseries C compiler library source file common to 78K/IV Series
(2) Flash memory writing tools
Flashpro II (Part number: FL-PR2), Flashpro III (Part number: FL-PR3, PG-FP3) FA-100GF FA-100GC Dedicated flash programmer for microcontroller incorporating flash memory
Adapter for writing 100-pin plastic QFP (GF-3BA type) flash memory. Connection must be performed in accordance with the target product. Adapter for writing 100-pin plastic LQFP (GC-8EU type) flash memory. Connection must be performed in accordance with the target product.
(3) Debugging tools * When IE-78K4-NS in-circuit emulator is used
IE-78K4-NS IE-70000-MC-PS-B IE-70000-98-IF-C IE-70000-CD-IF-A IE-70000-PC-IF-C IE-70000-PCI-IF IE-784225-NS-EM1 NP-100GF NP-100GC EV-9200GF-100 TGC-100SDW ID78K4-NS SM78K4 DF784218 In-circuit emulator common to 78K/IV Series Power supply unit for IE-78K4-NS Interface adapter required when PC-9800 series PC (except notebook type) is used as host machine (C bus supported) PC card and cable when PC-9800 series notebook PC is used as host machine (PCMCIA socket supported) Interface adapter required when using IBM PC/AT supported)
TM
compatibles as host machine (ISA bus
Interface adapter required when using PC that incorporates PCI bus as host machine Emulation board to emulate PD784216A, 784216AY, 784218A, 784218AY Subseries Emulation probe for 100-pin plastic QFP (GF-3BA type) Emulation probe for 100-pin plastic LQFP (GC-8EU type) Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type) Conversion adapter to connect the NP-100GC and a target system board on which a 100-pin plastic LQFP (GC-8EU type) can be mounted Integrated debugger for IE-78K4-NS System simulator common to 78K/IV Series Device file common to PD784216A, 784216AY, 784218A, 784218AY Subseries
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Data Sheet U14125EJ1V0DS00
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* When IE-784000-R in-circuit emulator is used
IE-784000-R IE-70000-98-IF-C IE-70000-PC-IF-C IE-70000-PCI-IF IE-78000-R-SV3 IE-784225-NS-EM1 IE-784000-R-EM IE-78K4-R-EX3 EP-784218GF-R EP-78064GC-R EV-9200GF-100 TGC-100SDW ID78K4 SM78K4 DF784218 In-circuit emulator common to 78K/IV Series Interface adapter required when PC-9800 series PC (except notebook type) is used as host machine (C bus supported) Interface adapter required when using IBM PC/AT and compatibles as host machine (ISA bus supported) Interface adapter required when using PC that incorporates PCI bus as host machine Interface adapter and cable required when EWS is used as host machine Emulation board to emulate PD784216A, 784216AY, 784218A, 784218AY Subseries Emulation board common to 78K/IV Series Emulation probe conversion board required when using IE-784225-NS-EM1 on IE-784000-R. Emulation probe for 100-pin plastic QFP (GF-3BA type) Emulation probe for 100-pin plastic LQFP (GC-8EU type) Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type) Conversion adapter to connect the EP-78064GC-R and a target system board on which a 100-pin plastic LQFP (GC-8EU type) can be mounted Integrated debugger for IE-784000-R System simulator common to 78K/IV Series Device file common to PD784216A, 784216AY, 784218A, 784218AY Subseries
(4) Real-time OS
RX78K/IV MX78K4 Real-time OS for 78K/IV Series OS for 78K/IV Series
Data Sheet U14125EJ1V0DS00
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PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
(5) Cautions on using development tools * The ID78K4-NS, ID78K4, and SM78K4 are used in combination with the DF784218. * The CC78K4 and RX78K/IV are used in combination with the RA78K4 and DF784218. * The FL-PR2, FL-PR3, FA-100GF, FA-100GC, NP-100GF, and NP-100GC are products made by Naito Densei Machida Mfg. Co., Ltd. (TEL: +81-44-822-3813). * The TGC-100SDW is a product made by TOKYO ELETECH CORPORATION. For further information, contact Daimaru Kogyo, Ltd. Tokyo Electronic Division (TEL: +81-3-3820-7112) Osaka Electronic Division (TEL: +81-6-6244-6672) * For third party development tools, see the Single-Chip Microcontroller Development Tool Selection Guide (U11069E). * The host machine and OS suitable for each software are as follows:
Host Machine [OS] Software RA78K4 CC78K4 ID78K4-NS ID78K4 SM78K4 RX78K/IV MX78K4 PC PC-9800 series [Windows] IBM PC/AT and compatibles [Japanese/English Windows] Note
Note
EWS HP9000 Series 700 [HP-UX ] TM TM TM SPARCstation [SunOS , Solaris ] TM TM NEWS (RISC) [NEWS-OS ] - -
TM TM

Note Note
Note DOS-based software
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Data Sheet U14125EJ1V0DS00
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APPENDIX B. RELATED DOCUMENTS
Documents related to devices
Document Name Document No. U14121E
PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Data Sheet PD78F4216A, 78F4216AY, 78F4218A, 78F4218AY Data Sheet PD784216A, 784216AY Subseries User's Manual Hardware PD784218A, 784218AY Subseries User's Manual Hardware
78K/IV Series User's Manual Instructions 78K/IV Series Instruction Table 78K/IV Series Instruction Set 78K/IV Series Application Note Software Basics
This document U13570E U12970E U10905E - - -
Documents related to development tools (user's manuals)
Document Name RA78K4 Assembler Package Language Operation RA78K Structured Assembler Preprocessor CC78K4 C Compiler Language Operation IE-78K4-NS IE-784000-R IE-784218-R-EM1 IE-784225-NS-EM1 EP-78064 SM78K4 System Simulator Windows Based SM78K Series System Simulator Reference External Part User Open Interface Specifications Reference Reference Reference Document No. U11162E U11334E U11743E U11571E U11572E U13356E U12903E U12155E U13742E EEU-1469 U10093E U10092E
ID78K4-NS Integrated Debugger PC Based ID78K4 Integrated Debugger Windows Based ID78K4 Integrated Debugger HP-UX, SunOS, NEWS-OS Based
U12796E U10440E U11960E
Caution
The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
Data Sheet U14125EJ1V0DS00
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PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Documents related to embedded software (user's manuals)
Document Name 78K/IV Series Real-Time OS Fundamental Installation Debugger 78K/IV Series OS MX78K4 Fundamental Document No. U10603E U10604E - -
Other documents
Document Name SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Guide to Microcomputer-Related Products by Third Party Document No. X13769X C10535E C11531E C10983E C11892E -
Caution
The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
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[MEMO]
Data Sheet U14125EJ1V0DS00
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[MEMO]
56
Data Sheet U14125EJ1V0DS00
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[MEMO]
Data Sheet U14125EJ1V0DS00
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NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
IEBus is a trademark of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation.
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Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Madrid Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore Tel: 65-253-8311 Fax: 65-250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Guarulhos-SP Brasil Tel: 55-11-6462-6810 Fax: 55-11-6462-6829
J00.7
Data Sheet U14125EJ1V0DS00
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PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Purchase of NEC I C components conveys a license under the Philips I C Patent Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips.
2 2
2
2
The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such.
* The information in this document is current as of August, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).
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